The extraction of parasitic circuit models is important for various aspects of physical verification such as timing, signal noise, and power grid analysis. Even though the recent processing technology advancements of copper interconnect reduces the effect of parasitic resistance and the low k (<3) dielectric material reduces the effect of parasitic capacitance, the continued scaling down of the feature size keeps the parasitic effects dominant, and makes it a necessity to account accurately for parasitic effects for large and complicated interconnect structures.
Parasitic extraction requires solving some form of Maxwell's equations with layout design and process profile data. Analytical formulas for simple or simplified geometry may be used where accuracy is less important than speed. However, numerical solution of the appropriate form of Maxwell's equation must be employed when the geometric configuration is not simple and accuracy demands do not allow simplification. The processor time and memory for numerically solving a differential form of or an integral form of the governing equations increase rapidly with the number of elements in the discretization of electromagnetic field. Fortunately, modern semiconductor designs are highly repetitive, either due to hierarchy or the use of programmatic layout generators. Parasitic elements extracted from such repetitive structures may demonstrate auto-correlation. It is thus advantageous to develop a method to optimize the parasitic extraction process based on the layout homotopy.